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1999 microchip technology inc. ds21163d-page 1 features ? voltage operating range: 4.5v to 5.5v - maximum write current 3 ma at 5.5v - standby current 1 m a typical at 5.0v ? 2-wire serial interface bus, i 2 c ? compatible ? 100 khz and 400 khz compatibility ? self-timed erase and write cycles ? power on/off data protection circuitry ? hardware write protect ? 1,000,000 erase/write cycles guaranteed ? 32-byte page or byte write modes available ? schmitt trigger filtered inputs for noise suppres- sion ? output slope control to eliminate ground bounce ? 2 ms typical write cycle time, byte or page ? up to eight devices may be connected to the same bus for up to 256k bits total memory ? electrostatic discharge protection > 4000v ? data retention > 200 years ? 8-pin pdip and soic packages ? temperature ranges description the microchip technology inc. 24c32a is a 4k x 8 (32k bit) serial electrically erasable prom. it has been developed for advanced, low power applications such as personal communications or data acquisition. the 24c32a also has a page-write capability of up to 32 bytes of data. the 24c32a is capable of both random and sequential reads up to the 32k boundary. func- tional address lines allow up to eight 24c32a devices on the same bus, for up to 256k bits address space. advanced cmos technology and broad voltage range make this device ideal for low-power/low-voltage, non- volatile code and data applications. the 24c32a is available in the standard 8-pin plastic dip and both 150 mil and 200 mil soic packaging. - commercial (c): 0c to 70c - industrial (i): -40c to +85c - automotive (e): -40c to +125c package types block diagram 24c32a 1 2 3 4 8 7 6 5 a0 a1 a2 vss vcc wp scl sda a0 a1 a2 vss 1 2 3 4 8 7 6 5 vcc wp scl sda pdip soic 24c32a hv generator eeprom array page latches ydec xdec sense amp r/w control memory control logic i/o control logic wp sda scl v cc v ss i/o a0 a1 a2 24c32a 32k 5.0v i 2 c ? serial eeprom i 2 c is a trademark of philips corporation.
24c32a ds21163d-page 2 1999 microchip technology inc. 1.0 electrical characteristics 1.1 maximum ratings* v cc ...................................................................................7.0v all inputs and outputs w.r.t. v ss ............... -0.6v to v cc +1.0v storage temperature ..................................... -65c to +150c ambient temp. with power applied ................-65c to +125c soldering temperature of leads (10 seconds) ............. +300c esd protection on all pins ..................................................3 4 kv *notice: stresses above those listed under maximum ratings may cause permanent damage to the device. this is a stress rat- ing only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. table 1-1: pin function table name function a0,a1,a2 user configurable chip selects v ss ground sda serial address/data i/o scl serial clock wp write protect input v cc +4.5v to 5.5v power supply table 1-2: dc characteristics figure 1-1: bus timing start/stop vcc = +4.5v to 5.5v commercial (c): tamb = 0 c to +70c industrial (i): tamb = -40c to +85c automotive(e): tamb = -40c to +125c parameter symbol min typ max units conditions a0, a1, a2, scl , sda and wp pins: high level input voltage v ih .7 v cc v low level input voltage v il .3 vccv hysteresis of schmitt trigger inputs v hys .05 v cc v(note) low level output voltage v ol .40vi ol = 3.0 ma input leakage current i li -10 10 m av in = .1v to v cc output leakage current i lo -10 10 m av out = .1v to v cc pin capacitance (all inputs/outputs) c in , c out 10pfv cc = 5.0v (note) tamb = 25c, f c = 1 mhz operating current i cc write 3 ma v cc = 5.5v, scl = 400 khz i cc read 0.5 ma v cc = 5.5v, scl = 400 khz standby current i ccs 1 5 m a scl = sda = v cc = 5.5v wp = v ss , a0, a1, a2 = v ss note: this parameter is periodically sampled and not 100% tested. scl sda t su : sta t hd : sta t su : sto v hys start stop
1999 microchip technology inc. ds21163d-page 3 24c32a table 1-3: ac characteristics figure 1-2: bus timing data parameter symbol vcc = 4.5-5.5 units remarks min max clock frequency f clk 100khz clock high time t high 4000 ns clock low time t low 4700 ns sda and scl rise time t r 1000 ns (note 1) sda and scl fall time t f 300 ns (note 1) start condition hold time t hd : sta 4000 ns after this period the first clock pulse is generated start condition setup time t su : sta 4700 ns only relevant for repeated start condition data input hold time t hd : dat 0ns data input setup time t su : dat 250 ns stop condition setup time t su : sto 4000 ns output valid from clock t aa 3500 ns (note 2) bus free time t buf 4700 ns time the bus must be free before a new transmission can start output fall time from v ih min to v il max t of 250 ns (note 1), c b 100 pf input filter spike suppression (sda and scl pins) t sp 50 ns (note 3) write cycle time t wr 5ms endurance 1m cycles 25c, vcc = 5.0v, block mode (note 4) note 1: not 100% tested. c b = total capacitance of one bus line in pf. 2: as a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 3: the combined t sp and v hys specifications are due to schmitt trigger inputs which provide improved noise and spike suppression. this eliminates the need for a ti specification for standard operation. 4: this parameter is not tested but guaranteed by characterization. for endurance estimates in a specific appli- cation, please consult the total endurance model which can be obtained on our website. scl sda in sda out t hd : sta t su : sta t f t high t r t su : sto t su : dat t hd : dat t buf t aa t hd : sta t aa t sp t low
24c32a ds21163d-page 4 1999 microchip technology inc. 2.0 functional description the 24c32a supports a bi-directional 2-wire bus and data transmission protocol. a device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. the bus must be controlled by a master device which generates the serial clock (scl), controls the bus access, and generates the start and stop conditions, while the 24c32a works as slave. both master and slave can operate as trans- mitter or receiver but the master device determines which mode is activated. 3.0 bus characteristics the following bus protocol has been defined: ? data transfer may be initiated only when the bus is not busy. ? during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as a start or stop condition. accordingly, the following bus conditions have been defined (figure 3-1). 3.1 bus not busy (a) both data and clock lines remain high. 3.2 start data transfer (b) a high to low transition of the sda line while the clock (scl) is high determines a start condition. all commands must be preceded by a start condition. 3.3 stop data transfer (c) a low to high transition of the sda line while the clock (scl) is high determines a stop condition. all operations must be ended with a stop condition. 3.4 data valid (d) the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. the number of the data bytes transferred between the start and stop conditions is determined by the master device. 3.5 acknowledge each receiving device, when addressed, is obliged to generate an acknowledge signal after the reception of each byte. the master device must generate an extra clock pulse which is associated with this acknowledge bit. a device that acknowledges must pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. dur- ing reads, a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave (24c32a) will leave the data line high to enable the master to generate the stop condition. note: the 24c32a does not generate any acknowledge bits if an internal program- ming cycle is in progress. figure 3-1: data transfer sequence on the serial bus scl sda (a) (b) (d) (d) (c) (a) start condition address or acknowledge valid data allowed to change stop condition
1999 microchip technology inc. ds21163d-page 5 24c32a 3.6 device addressing a control byte is the first byte received following the start condition from the master device. the control byte consists of a 4-bit control code; for the 24c32a this is set as 1010 binary for read and write (r/w ) operations. the next three bits of the control byte are the device select bits (a2, a1, a0). they are used by the master device to select which of the eight devices are to be accessed. these bits are in effect the three most signif- icant bits of the word address. the last bit of the control byte defines the operation to be performed. when set to a one a read operation is selected, and when set to a zero a write operation is selected. the next two bytes received define the address of the first data byte (figure 3-3). because only a11...a0 are used, the upper four address bits must be zeros. the most signif- icant bit of the most significant byte of the address is transferred first. figure 3-2: control byte allocation r/w a 1 0 1 0 a2 a1 a0 read/write start slave address following the start condition, the 24c32a monitors the sda bus checking the device type identifier being transmitted. upon receiving a 1010 code and appropri- ate device select bits, the slave device outputs an acknowledge signal on the sda line. depending on the state of the r/w bit, the 24c32a will select a read or write operation. operation control code device select r/w read 1010 device address 1 write 1010 device address 0 figure 3-3: address sequence bit assignments 1010 a 2 a 1 a 0 r/w 0000 a 11 a 10 a 9 a 7 a 0 a 8 slave address device select bus control byte address byte 1 address byte 0
24c32a ds21163d-page 6 1999 microchip technology inc. 4.0 write operation 4.1 byte write following the start condition from the master, the con- trol code (four bits), the device select (three bits), and the r/w bit which is a logic low are clocked onto the bus by the master transmitter. this indicates to the addressed slave receiver that a byte with a word address will follow after it has generated an acknowl- edge bit during the ninth clock cycle. therefore, the next byte transmitted by the master is the high-order byte of the word address and will be written into the address pointer of the 24c32a. the next byte is the least significant address byte. after receiving another acknowledge signal from the 24c32a the master device will transmit the data word to be written into the addressed memory location. the 24c32a acknowledges again and the master gen- erates a stop condition. this initiates the internal write cycle, and during this time the 24c32a will not gener- ate acknowledge signals (figure 4-1). 4.2 page write the write control byte, word address and the first data byte are transmitted to the 24c32a in the same way as in a byte write. but instead of generating a stop condi- tion, the master transmits up to 32 bytes which are tem- porarily stored in the on-chip page buffer and will be written into memory after the master has transmitted a stop condition. after receipt of each word, the five lower address pointer bits are internally incremented by one. if the master should transmit more than 32 bytes prior to generating the stop condition, the address counter will roll over and the previously received data will be overwritten. as with the byte write operation, once the stop condition is received, an internal write cycle will begin. (figure 4-2). note: page write operations are limited to writing bytes within a single physical page, regard- less of the number of bytes actually being written. physical page boundaries start at addresses that are integer multiples of the page buffer size (or page size) and end at addresses that are integer multiples of [page size - 1]. if a page write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. it is therefore neces- sary for the application software to prevent page write operations that would attempt to cross a page boundary. figure 4-1: byte write figure 4-2: page write 0000 bus activity master sda line bus activity s t a r t control byte address high byte address low byte data a c k a c k a c k a c k s t o p s p 0000 bus activity master sda line bus activity s t a r t control byte address high byte address low byte data byte 0 a c k a c k a c k a c k s t o p data byte 31 s p
1999 microchip technology inc. ds21163d-page 7 24c32a 5.0 acknowledge polling since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). once the stop condition for a write com- mand has been issued from the master, the device ini- tiates the internally timed write cycle. acknowledge polling (ack) can be initiated immediately. this involves the master sending a start condition followed by the control byte for a write command (r/w = 0). if the device is still busy with the write cycle, then no ack will be returned. if the cycle is complete, then the device will return the ack and the master can then pro- ceed with the next read or write command. see figure 5-1 for flow diagram. figure 5-1: acknowledge polling flow send write command send stop condition to initiate write cycle send start send control byte with r/w = 0 did device acknowledge (ack = 0)? next operation no yes 6.0 read operation read operations are initiated in the same way as write operations with the exception that the r/w bit of the slave address is set to one. there are three basic types of read operations: current address read, random read, and sequential read. 6.1 current address read the 24c32a contains an address counter that main- tains the address of the last word accessed, internally incremented by one. therefore, if the previous access (either a read or write operation) was to address n (n is any legal address), the next current address read oper- ation would access data from address n + 1. upon receipt of the slave address with r/w bit set to one, the 24c32a issues an acknowledge and transmits the eight bit data word. the master will not acknowledge the transfer but does generate a stop condition and the 24c32a discontinues transmission (figure 6-1). 6.2 random read random read operations allow the master to access any memory location in a random manner. to perform this type of read operation, first the word address must be set. this is done by sending the word address to the 24c32a as part of a write operation (r/w bit set to zero). after the word address is sent, the master gen- erates a start condition following the acknowledge. this terminates the write operation, but not before the inter- nal address pointer is set. then the master issues the control byte again but with the r/w bit set to a one. the 24c32a will then issue an acknowledge and transmit the 8-bit data word. the master will not acknowledge the transfer but does generate a stop condition which causes the 24c32a to discontinue transmission (figure 6-2). figure 6-1: current address read sp bus activity master sda line bus activity s t a r t control byte data byte s t o p a c k n o a c k
24c32a ds21163d-page 8 1999 microchip technology inc. 6.3 contiguous addressing across multiple devices the device select bits a2, a1, a0 can be used to expand the contiguous address space for up to 256k bits by adding up to eight 24c32a's on the same bus. in this case, software can use a0 of the control byte as address bit a12, a1 as address bit a13, and a2 as address bit a14. 6.4 sequential read sequential reads are initiated in the same way as a ran- dom read except that after the 24c32a transmits the first data byte, the master issues an acknowledge as opposed to the stop condition used in a random read. this acknowledge directs the 24c32a to transmit the next sequentially addressed 8-bit word (figure 6-3). following the final byte transmitted to the master, the master will not generate an acknowledge but will gen- erate a stop condition. to provide sequential reads the 24c32a contains an internal address pointer which is incremented by one at the completion of each operation. this address pointer allows the entire memory contents to be serially read during one operation. the internal address pointer will automatically roll over from address 0fff to address 000 if the master acknowledges the byte received from the array address 0fff. figure 6-2: random read figure 6-3: sequential read 0000 bus activity master sda line bus activity s t a r t control s t o p a c k n o a c k byte address high byte address low byte control byte data byte a c k a c k a c k s t a r t s sp bus activity master sda line bus activity control byte a c k n o a c k a c k a c k a c k data n data n + 1 data n + 2 data n + x s t o p p
1999 microchip technology inc. ds21163d-page 9 24c32a 7.0 pin descriptions 7.1 a0, a1, a2 chip address inputs the a0..a2 inputs are used by the 24c32a for multiple device operation and conform to the 2-wire bus stan- dard. the levels applied to these pins define the address block occupied by the device in the address map. a particular device is selected by transmitting the corresponding bits (a2, a1, a0) in the control byte (figure 3-3). 7.2 sda serial address/data input/output this is a bi-directional pin used to transfer addresses and data into and data out of the device. it is an open drain terminal, therefore the sda bus requires a pullup resistor to v cc (typical 10k w for 100 khz, 2 k w for 400 khz) for normal data transfer sda is allowed to change only during scl low. changes during scl high are reserved for indicating the start and stop condi- tions. 7.3 scl serial clock this input is used to synchronize the data transfer from and to the device. 7.4 wp this pin must be connected to either v ss or v cc . if tied to v ss , normal memory operation is enabled (read/write the entire memory 000-fff). if tied to v cc , write operations are inhibited. the entire memory will be write-protected. read operations are not affected. 8.0 noise protection the scl and sda inputs have filter circuits which sup- press noise spikes to ensure proper device operation even on a noisy bus. all i/o lines incorporate schmitt triggers for 400 khz (fast mode) compatibility. 9.0 power management this design incorporates a power standby mode when the device is not in use and automatically powers off after the normal termination of any operation when a stop bit is received and all internal functions are com- plete. this includes any error conditions, i.e., not receiving an acknowledge or stop condition per the two-wire bus specification. the device also incorpo- rates v dd monitor circuitry to prevent inadvertent writes (data corruption) during low-voltage conditions. the v dd monitor circuitry is powered off when the device is in standby mode in order to further reduce power con- sumption.
24c32a ds21163d-page 10 1999 microchip technology inc. notes:
24c32a 24c32a product identification system to order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory o r the listed sales offices. sales and support data sheets products supported by a preliminary data sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: 1. your local microchip sales office 2. the microchip corporate literature center u.s. fax: (602) 786-7277 3. the microchip worldwide site (www.microchip.com) please specify which device, revision of silicon and data sheet (include literature #) you are using. new customer notification system register on our web site (www.microchip.com/cn) to receive the most current information on our products. package: p = plastic dip (300 mil body), 8-lead sn = plastic soic (150 mil body, eiaj standard) sm = plastic soic (207 mil body, eiaj standard) temperature blank = 0 c to +70 c range: i =-40 c to +85 c e = -40 c to +125 c device: 24c32a 32k i 2 c serial eeprom (100 khz, 400 khz) 24c32at 32k i 2 c serial eeprom (tape and reel) 24c32a - /p 1999 microchip technology inc. ds21163d-page 11
information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. no representation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patents or oth er intellectual property rights arising from such use or otherwise. use of microchip?s products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, under any intellectual property rights. the microchip logo and name are registered trademarks of microchip technology inc. in the u.s.a. and other countries. all rights reserved. al l other trademarks mentioned herein are the property of their respective companies. ? 1999 microchip technology inc. all rights reserved. ? 1999 microchip technology incorporated. printed in the usa. 11/99 printed on recycled paper. americas corporate office microchip technology inc. 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-786-7200 fax: 480-786-7277 technical support: 480-786-7627 web address: http://www.microchip.com atlanta microchip technology inc. 500 sugar mill road, suite 200b atlanta, ga 30350 tel: 770-640-0034 fax: 770-640-0307 boston microchip technology inc. 5 mount royal avenue marlborough, ma 01752 tel: 508-480-9990 fax: 508-480-8575 chicago microchip technology inc. 333 pierce road, suite 180 itasca, il 60143 tel: 630-285-0071 fax: 630-285-0075 dallas microchip technology inc. 4570 westgrove drive, suite 160 addison, tx 75248 tel: 972-818-7423 fax: 972-818-2924 dayton microchip technology inc. two prestige place, suite 150 miamisburg, oh 45342 tel: 937-291-1654 fax: 937-291-9175 detroit microchip technology inc. tri-atria office building 32255 northwestern highway, suite 190 farmington hills, mi 48334 tel: 248-538-2250 fax: 248-538-2260 los angeles microchip technology inc. 18201 von karman, suite 1090 irvine, ca 92612 tel: 949-263-1888 fax: 949-263-1338 new york microchip technology inc. 150 motor parkway, suite 202 hauppauge, ny 11788 tel: 631-273-5305 fax: 631-273-5335 san jose microchip technology inc. 2107 north first street, suite 590 san jose, ca 95131 tel: 408-436-7950 fax: 408-436-7955 americas (continued) toronto microchip technology inc. 5925 airport road, suite 200 mississauga, ontario l4v 1w1, canada tel: 905-405-6279 fax: 905-405-6253 asia/pacific hong kong microchip asia pacific unit 2101, tower 2 metroplaza 223 hing fong road kwai fong, n.t., hong kong tel: 852-2-401-1200 fax: 852-2-401-3431 beijing microchip technology, beijing unit 915, 6 chaoyangmen bei dajie dong erhuan road, dongcheng district new china hong kong manhattan building beijing 100027 prc tel: 86-10-85282100 fax: 86-10-85282104 india microchip technology inc. india liaison office no. 6, legacy, convent road bangalore 560 025, india tel: 91-80-229-0061 fax: 91-80-229-0062 japan microchip technology intl. inc. benex s-1 6f 3-18-20, shinyokohama kohoku-ku, yokohama-shi kanagawa 222-0033 japan tel: 81-45-471- 6166 fax: 81-45-471-6122 korea microchip technology korea 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku seoul, korea tel: 82-2-554-7200 fax: 82-2-558-5934 shanghai microchip technology rm 406 shanghai golden bridge bldg. 2077 yan?an road west, hong qiao district shanghai, prc 200335 tel: 86-21-6275-5700 fax: 86 21-6275-5060 asia/pacific (continued) singapore microchip technology singapore pte ltd. 200 middle road #07-02 prime centre singapore 188980 tel: 65-334-8870 fax: 65-334-8850 taiwan, r.o.c microchip technology taiwan 10f-1c 207 tung hua north road ta i p e i , ta i wa n , ro c tel: 886-2-2717-7175 fax: 886-2-2545-0139 europe united kingdom arizona microchip technology ltd. 505 eskdale road winnersh triangle wokingham berkshire, england rg41 5tu tel: 44 118 921 5858 fax: 44-118 921-5835 denmark microchip technology denmark aps regus business centre lautrup hoj 1-3 ballerup dk-2750 denmark tel: 45 4420 9895 fax: 45 4420 9910 france arizona microchip technology sarl parc d?activite du moulin de massy 43 rue du saule trapu batiment a - ler etage 91300 massy, france tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany arizona microchip technology gmbh gustav-heinemann-ring 125 d-81739 mnchen, germany tel: 49-89-627-144 0 fax: 49-89-627-144-44 italy arizona microchip technology srl centro direzionale colleoni palazzo taurus 1 v. le colleoni 1 20041 agrate brianza milan, italy tel: 39-039-65791-1 fax: 39-039-6899883 11/15/99 w orldwide s ales and s ervice microchip received qs-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona in july 1999. the company?s quality system processes and procedures are qs-9000 compliant for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms and microperipheral products. in addition, microchip ? s quality system for the design and manufacture of development systems is iso 9001 certified.

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